1. Field
The present disclosure relates to a delta-sigma modulator.
2. Description of Related Art
Discrete-time (DT) delta-sigma modulators (hereinafter abbreviated as “DSM”) are widely used in high resolution audio and middle-low speed radio receiver applications due to features such as insensitivity to a clock jitter, accurate filter coefficient, a scalability of a clock frequency, as compared with a continuous-time DSM. In the DT DSM using a switched capacitor integrator (hereinafter, referred to as an SC integrator), a double sampling technique for effectively doubling an oversampling ratio (hereinafter, abbreviated as OSR) without being bound to OP amp settling requirement has been used.
Despite the advantage of the doubled OSR, the double-sampled DSM has a problem of noise folding due to a mismatch between the feedback digital-analog converter (DAC) paths.
As one method for avoiding the noise folding, a method which uses a single capacitor in two feedback paths has been suggested. When this method is used, the mismatch problem does not occur.
However, the method has a disadvantage in that it cannot allow a configuration in which the sampling capacitor is shared by input and feedback DAC signals. Such a restriction causes a silicon area to be increased because of increased kT/C noise, higher bias current of the OP-amp, the doubled sampling, and integrated capacitors.
As another method for avoiding the problems of noise folding, there is a method that uses a modified noise transfer function (NTF) technique. In the modified noise transfer technique, zero is added to reduce a shaped quantization noise near fs/2. Such a technique may minimize a noise folding amount and adopt input-sampling sharing structure so that it is possible to achieve the reduced kT/C noise, a lower OP-amp bias current, and a smaller silicon area.
However, (1+z−1) of the NTF may deteriorate a signal-to-quantization noise ratio (SQNR) by 6 dB per zero and a complex double sampled resonator for implementing zero at fs/2 causes higher overheads in terms of power and silicon area used.